of "class", so that it matches the subsequent definition.

llvm-svn: 70498

Fix multiclass inheritance to limit value resolution to new defs added
by base multiclasses.  Do not attempt to alter defs from previous base
multiclasses.  This fixes multiple multiclass inheritance.

llvm-svn: 69974

Make BinOps typed and require a type specifier for !nameconcat.  This
allows binops to be used in typed contexts such as when passing
arguments to classes.

llvm-svn: 69921

Implement !nameconcat to concatenate strings and look up the resulting
name in the symbol table, returning an object.

llvm-svn: 69822

in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.

llvm-svn: 67286

llvm-svn: 66970

errors when thrown.  This gets us nice errors like this from tblgen:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: error:
Included from X86.td:116:
Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands!
def CMOVL32rr : I<0x4C, MRMSrcReg,       // if <s, GR32 = GR32
^

instead of just:

CMOVL32rr: 	(set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands!

This is all I plan to do with this, but it should be easy enough to improve if anyone 
cares (e.g. keeping more loc info in "dag" expr records in tblgen.

llvm-svn: 66898

llvm-svn: 66897

-Bring in int64_t for TableGen/Record.h and TableGen/TGLexer.h
-Define strtoull

llvm-svn: 57970

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

by its first field, but TableGen doesn't actually enforce creating it that 
way. TableGen sorts the records that will be used to create it by the names 
of the records, not the Name field of those records.

This patch corrects the sort to use the "Name" field of the record as the 
sort key.

llvm-svn: 56106

orders, part of PR2590

llvm-svn: 55359

llvm-svn: 53179

llvm-svn: 48801

llvm-svn: 46250

llvm-svn: 46223

llvm-svn: 45419

print in terms of that.

llvm-svn: 44276

llvm-svn: 44275

llvm-svn: 44257

llvm-svn: 43993

llvm-svn: 37063

llvm-svn: 34697

CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h

llvm-svn: 34693

llvm-svn: 34682

llvm-svn: 32333

llvm-svn: 29930

operation.  This implements Regression/TableGen/strconcat.td.

llvm-svn: 27312

llvm-svn: 27263

llvm-svn: 25836

reflect what it is.
Convert some more code over to use it.

llvm-svn: 24072

simplifies using list of records.

llvm-svn: 24069

methods.  Use it to simplify some code.

llvm-svn: 23336

llvm-svn: 22912

llvm-svn: 22911

llvm-svn: 21441

llvm-svn: 21428

finished up, only resolve fully when the def is defined.  This allows things
to be changed and all uses to be propagated through.  This implements
TableGen/LazyChange.td and fixes TemplateArgRename.td in the process.

None of the .td files used in LLVM backends are changed at all by this
patch.

llvm-svn: 21344

llvm-svn: 21336

will lead to it being rejected though.

llvm-svn: 21335