It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility.  The symbols are removed by the linker from the final linked image
(executable or dynamic library).

llvm-svn: 111684

zero-extend operations.

llvm-svn: 111614

move some constraints around.

llvm-svn: 111594

llvm-svn: 111592

llvm-svn: 111585

rdar://8277890

llvm-svn: 111533

llvm-svn: 111518

call and jumps.

llvm-svn: 111496

llvm-svn: 111494

llvm-svn: 111489

llvm-svn: 111481

llvm-svn: 111468

llvm-svn: 111456

frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.

rdar://8277890

llvm-svn: 111443

llvm-svn: 111430

llvm-svn: 111383

Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890

llvm-svn: 111374

The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.

llvm-svn: 111361

The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.

llvm-svn: 111360

"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.

llvm-svn: 111358

llvm-svn: 111345

llvm-svn: 111343

Testcase from Nick Lewycky.

llvm-svn: 111341

the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.

llvm-svn: 111315

llvm-svn: 111291

  - Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

llvm-svn: 111289

Patch by Cameron Esfahani!

llvm-svn: 111288

llvm-svn: 111277

llvm-svn: 111266

Modernize predicates a bit.

The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.

llvm-svn: 111263

whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890

llvm-svn: 111262

llvm-svn: 111260

printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251

llvm-svn: 111241

llvm-svn: 111226

we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222

llvm-svn: 111219

llvm-svn: 111208

that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196

llvm-svn: 111185