llvm-svn: 27257

llvm-svn: 27256

llvm-svn: 27255

For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250

integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248

- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

- Other shuffle related fixes.

llvm-svn: 27244

The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240

llvm-svn: 27221

llvm-svn: 27219

* Bug fixes.

llvm-svn: 27218

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27174

llvm-svn: 27167

llvm-svn: 27150

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27103

llvm-svn: 27096

llvm-svn: 27094

llvm-svn: 27091

llvm-svn: 27087

llvm-svn: 27083

llvm-svn: 27056

llvm-svn: 27040

llvm-svn: 27024

llvm-svn: 26980

llvm-svn: 26969

llvm-svn: 26967

llvm-svn: 26959

- Don't forget pshufd is only available with sse2.

llvm-svn: 26956

  splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954

  PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951

llvm-svn: 26949

llvm-svn: 26940

- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932

- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919

llvm-svn: 26911