llvm-svn: 141728

llvm-svn: 141727

The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.

I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.

llvm-svn: 141726

llvm-svn: 141722

Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721

llvm-svn: 141720

the real instructions.

llvm-svn: 141718

llvm-svn: 141716

llvm-svn: 141715

would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

llvm-svn: 141713

llvm-svn: 141708

We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

llvm-svn: 141704

lying around...

llvm-svn: 141703

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689

Expose MachOObjectFile externally, like we do for COFF.  First step in reducing the amount of special-purpose code needed for llvm-objdump.

llvm-svn: 141684

llvm-svn: 141682

llvm-svn: 141671

llvm-svn: 141667

This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).

llvm-svn: 141666

llvm-svn: 141665

Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32)

llvm-svn: 141661

llvm-svn: 141659

llvm-svn: 141656

llvm-svn: 141654

llvm-svn: 141651

lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

llvm-svn: 141646

Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.

llvm-svn: 141642

.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641

in st_shndx fields.

llvm-svn: 141639

layer of abstraction around SymbolRef where you can read its private
SymbolPimpl member.

llvm-svn: 141636

I'm not sure we will need it in the long run, but the option is
currently useful for checking if the output of LSR is "clean".

llvm-svn: 141634

IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.

llvm-svn: 141633

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

llvm-svn: 141619

Mips64.

llvm-svn: 141618

llvm-svn: 141616

llvm-svn: 141615