llvm-svn: 89245

forward declaration and patching tblgen to emit it right. Patch by Amine Khaldi!

llvm-svn: 88798

Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.

llvm-svn: 88753

llvm-svn: 86797

since the instruction might use the other result of different type.

llvm-svn: 86462

llvm-svn: 86239

llvm-svn: 86206

llvm-svn: 85910

Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.

PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766

llvm-svn: 85556

*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.

llvm-svn: 85530

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

I was trying to check the WIP file to some local repository, but ended up
checking in the llvm repository.  Oops!

llvm-svn: 85470

declaring local variables.

llvm-svn: 85467

llvm-svn: 85215

direct inclusion edge from System to Support.

llvm-svn: 85086

llvm-svn: 84827

Useful for OptionPreprocessor.

llvm-svn: 84728

llvm-svn: 84537

llvm-svn: 84450

llvm-svn: 84358

llvm-svn: 84356

More to follow...

llvm-svn: 84352

llvm-svn: 84351

Several instances of PluginPriority in a single file most probably signifies a
programming error.

llvm-svn: 84350

llvm-svn: 84193

llvm-svn: 83619

Important, for example, when calling 'gcc a.o b.o c.o -lD -lE -lF'.

llvm-svn: 83524

set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.

llvm-svn: 83196

unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006

llvm-svn: 82957

llvm-svn: 82955

 - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790

llvm-svn: 82709

llvm-svn: 82456

llvm-svn: 82244

llvm-svn: 82236

llvm-svn: 81742

llvm-svn: 81741