llvm-svn: 131106

Patch by Evan Cheng.

llvm-svn: 131093

llvm-svn: 131082

It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register.  If the allocated register doesn't support the sub-register index,
just use %noreg for the debug variables instead of asserting.

In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD
register. The register is split and one part is inflated to GR32 and assigned
%ESI because there are no more normal uses of sub_8bit_hi.

Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will
simply insert a %noreg instead, and the debug variable will be marked
unavailable in that range.

We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I
don't know if DWARF even supports that.

llvm-svn: 131073

This can't be just an assertion, users can always write impossible inline
assembly. Such an assembly statement should be included in the error message.

llvm-svn: 131024

llvm-svn: 131022

llvm-svn: 131015

llvm-svn: 131012

llvm-svn: 131008

This should unbreak dragonegg-i386-linux and build-self-4-mingw32.

llvm-svn: 131007

llvm-svn: 131001

After a virtual register is split, update any debug user variables that resided
in the old register. This ensures that the LiveDebugVariables are still correct
after register allocation.

This may create DBG_VALUE instructions that place a user variable in a register
in parts of the function and in a stack slot in other parts. DwarfDebug
currently doesn't support that.

llvm-svn: 130998

llvm-svn: 130997

llvm-svn: 130996

The post-ra scheduler was explicitly updating the depth of a node's
successors after scheduling it, regardless of whether the successor
was ready. This is quadratic for DAGs with transitively redundant
edges. I simply removed the useless update of depth, which is lazilly
computed later.
Fixes <rdar://problem/9044332> compiler takes way too long to build TextInput.

llvm-svn: 130992

Move CompileUnit::getOrCreateNameSpace() and CompileUnit::addPubType() from DwarfDebug.cpp to DwarfCompileUnit.cpp

llvm-svn: 130991

llvm-svn: 130989

llvm-svn: 130988

llvm-svn: 130987

llvm-svn: 130985

llvm-svn: 130984

possibly related to cbnz formation.

llvm-svn: 130977

llvm-svn: 130964

llvm-svn: 130959

llvm-svn: 130955

llvm-svn: 130947

llvm-svn: 130944

BuildSchedGraph was quadratic in the number of calls in the basic
block. After this fix, it keeps only a single call at the top of the
DefList so compile time doesn't blow up on large blocks. This reduces
postRA sched time on an external test case from 81s to 0.3s.  Although
r130800 (reduced ARM register alias defs) also partially fixes the
issue by reducing the constant overhead of checking call interference
by an order of magnitude.

Fixes <rdar://problem/7662664> very poor compile time with post RA scheduling.

llvm-svn: 130943

llvm-svn: 130942

llvm-svn: 130934

llvm-svn: 130933

llvm-svn: 130931

Avoid extra vreg copies for arguments passed in registers.  Specifically, this can make MachineCSE more effective in some cases (especially in small functions).  PR8361 / part of rdar://problem/8259436 .

llvm-svn: 130928

llvm-svn: 130926

llvm-svn: 130925

who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>

llvm-svn: 130918

Joining physregs is inherently dangerous because it uses a heuristic to avoid
creating invalid code. Linear scan had an emergency spilling mechanism to deal
with those rare cases. The new greedy allocator does not.

The greedy register allocator is much better at taking hints, so this has almost
no impact on code size and quality. The few cases where it matters show up as
unit tests that now have -join-physregs enabled explicitly.

llvm-svn: 130896

landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>

llvm-svn: 130881

Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877

llvm-svn: 130867