llvm-svn: 115156

llvm-svn: 115154

for the dwarf .loc support to emit dwarf line number tables.

llvm-svn: 115153

llvm-svn: 115149

llvm-svn: 115147

llvm-svn: 115136

llvm-svn: 115135

With this patch in

movq    $foo, foo(%rip)
foo:
.long   foo

We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.

llvm-svn: 115134

Small test for sanity check of resulting ARM .s file.
Tested against -r115129.

llvm-svn: 115133

Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.

llvm-svn: 115130

I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)

Tested against -r115126

llvm-svn: 115129

to an empty PrintSpecial()

llvm-svn: 115128

(Kill the dead non-MC asm printer for the ARM target.)

llvm-svn: 115127

1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121

llvm-svn: 115116

for generic call handling.

llvm-svn: 115105

llvm-svn: 115100

pipeline forwarding path.

llvm-svn: 115098

a context.

llvm-svn: 115094

which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.

llvm-svn: 115066

  lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'

llvm-svn: 115064

llvm-svn: 115061

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047

llvm-svn: 115043

One Printer to lower them all and in the back end bind them.


(Remove option to use the old non-MC asm printer.)

llvm-svn: 115038

added some doxygen on the way

llvm-svn: 115033

llvm-svn: 115029

llvm-svn: 115027

order as cctools for diffability.

llvm-svn: 115022

are defined to emit the 0x67 prefix byte.  rdar://8482675

llvm-svn: 115021

operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up.  This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'

llvm-svn: 115019

Clean up cvttps2dq by removing some redundant implementations of the
same instruction.  rdar://8456382

llvm-svn: 115018

llvm-svn: 115017

an instruction that requires a WHOLE NEW wonderful kind of alias.

llvm-svn: 115015

MCStreamer to emit into instead of an MCInst to fill in.  This allows the
matcher extra flexibility and is more convenient.

llvm-svn: 115014

problems with phi-nodes in blocks that have hard and not virtual registers.

Accordingly update branch handling to compensate.

llvm-svn: 115013

llvm-svn: 115011

llvm-svn: 115010

llvm-svn: 115009

Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.

llvm-svn: 115008