allowing the memcpy to be eliminated.

Unfortunately, the requirements on byval's without explicit 
alignment are really weak and impossible to predict in the 
mid-level optimizer, so this doesn't kick in much with current
frontends.  The fix is to change clang to set alignment on all
byval arguments.

llvm-svn: 119916

llvm-svn: 119913

mode variables. Handle frame indexes in load/store and allocas again.

llvm-svn: 119912

to match the one from the load emitter above.

llvm-svn: 119911

llvm-svn: 119908

llvm-svn: 119905

llvm-svn: 119904

llvm-svn: 119903

so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901

Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.

llvm-svn: 119898

llvm-svn: 119896

llvm-svn: 119895

llvm-svn: 119883

llvm-svn: 119882

llvm-svn: 119881

value that the one in ARMMCCodeEmitter.cpp does.

llvm-svn: 119878

llvm-svn: 119875

llvm-svn: 119869

llvm-svn: 119868

llvm-svn: 119867

llvm-svn: 119866

llvm-svn: 119865

llvm-svn: 119864

llvm-svn: 119863

llvm-svn: 119862

llvm-svn: 119861

asm parser can handle them.

llvm-svn: 119860

llvm-svn: 119859

llvm-svn: 119858

should give allow a wider range of addressing modes.

No functional change.

llvm-svn: 119856

llvm-svn: 119855

if all the operands of the PHI are equivalent.  This allows CodeGenPrepare to undo
unprofitable PRE transforms.

llvm-svn: 119853

llvm-svn: 119852

llvm-svn: 119851

llvm-svn: 119850

initialize missing bit.

llvm-svn: 119849

llvm-svn: 119846

llvm-svn: 119844

llvm-svn: 119843

llvm-svn: 119842