can terminate a block with no fall-through.

llvm-svn: 42029

llvm-svn: 41975

llvm-svn: 41962

Patch by Sterling Stein!

llvm-svn: 41758

leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40537

llvm-svn: 37960

their names are changed.

llvm-svn: 37876

model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37578

implementation for x86.

llvm-svn: 37576

llvm-svn: 37571

llvm-svn: 37528

llvm-svn: 37266

llvm-svn: 37193

llvm-svn: 36430

llvm-svn: 36404

llvm-svn: 35638

llvm-svn: 35616

_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret

llvm-svn: 35434

system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204

moves, loads, etc. are recognized.

llvm-svn: 35031

llvm-svn: 33537

convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.

llvm-svn: 32097

of opcode and number of operands.

llvm-svn: 31947

llvm-svn: 31794

llvm-svn: 31765

llvm-svn: 31712

llvm-svn: 31298

llvm-svn: 31262

llvm-svn: 31099

llvm-svn: 31097

llvm-svn: 31095

llvm-svn: 31093

llvm-svn: 31074

llvm-svn: 31065