Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

llvm-svn: 120892

foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889

llvm-svn: 120865

tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858

llvm-svn: 120857

operand encoding ordering of the instruction.

llvm-svn: 120852

ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849

halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848

I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847

llvm-svn: 120844

it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843

32-bit wide version by adding the .w suffix.

llvm-svn: 120838

llvm-svn: 120836

immediate offset.

llvm-svn: 120833

llvm-svn: 120832

llvm-svn: 120831

llvm-svn: 120824

llvm-svn: 120822

llvm-svn: 120782

llvm-svn: 120780

data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

llvm-svn: 120767

<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766

llvm-svn: 120748

This is a fix for llvm-gcc-i386-darwin9 buildbot failure.

llvm-svn: 120742

not thumb2.

llvm-svn: 120711

llvm-svn: 120709

llvm-svn: 120707

pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635

llvm-svn: 120630

llvm-svn: 120622

llvm-svn: 120619

encoding if we're in that mode.

llvm-svn: 120608

llvm-svn: 120604

instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594

Add correct encodings for STRD and LDRD, including fixup support.  Additionally, update these to unified syntax.

llvm-svn: 120589

llvm-svn: 120586

llvm-svn: 120584

llvm-svn: 120580

The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.

llvm-svn: 120574

llvm-svn: 120571