yet, only assembly encoding support.

llvm-svn: 105521

llvm-svn: 105519

should be calling it.

llvm-svn: 105517

unless using -arm-tail-calls.

llvm-svn: 105515

llvm-svn: 105514

llvm-svn: 105513

llvm-svn: 105511

there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510

I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509

llvm-svn: 105508

Radar 8055687.

llvm-svn: 105505

llvm-svn: 105502

register pressure.

llvm-svn: 105501

llvm-svn: 105498

llvm-svn: 105496

llvm-svn: 105495

llvm-svn: 105492

Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.

llvm-svn: 105490

llvm-svn: 105488

llvm-svn: 105485

llvm-svn: 105481

llvm-svn: 105480

register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473

8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472

llvm-svn: 105470

llvm-svn: 105461

llvm-svn: 105456

llvm-svn: 105454

replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453

llvm-svn: 105450

functions where they belong.

llvm-svn: 105449

Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443

llvm-svn: 105442

llvm-svn: 105441

llvm-svn: 105440

VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

llvm-svn: 105439

llvm-svn: 105438

Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

llvm-svn: 105437

llvm-svn: 105435

llvm-svn: 105427