Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.

llvm-svn: 198530

Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time.

llvm-svn: 198529

Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.

llvm-svn: 198515

Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.

llvm-svn: 198475

llvm-svn: 198449

A ValueType in a pattern dag is a type cast, and GetNumNodeResults should
handle it (the type cast has only one result).

This comes up, for example, during the type checking of pattern fragments, for
example, AArch64's Neon_combine_2d fragment is:
  dag Operands = (ops node:$Rm, node:$Rn);
  dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn)));

llvm-svn: 198347

llvm-svn: 198336

llvm-svn: 198332

Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.

llvm-svn: 198327

llvm-svn: 198325

Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.

llvm-svn: 198323

llvm-svn: 198291

Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.

llvm-svn: 198284

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

llvm-svn: 198278

Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277

Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198276

Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.

llvm-svn: 198265

Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198238

Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change.

llvm-svn: 198226

Simplify filter accepts function to just return 'condition' instead of branching to return true/false. No functional change.

llvm-svn: 198221

llvm-lit can be invoked;

  $ Release/bin/llvm-lit

instead of;

  $ bin/llvm-lit --param buid_mode=Release

llvm-svn: 198206

Remove the stat call error reporting for now.

It wasn't essential so silent fallback should be fine here.

llvm-svn: 198155

llvm-svn: 198152

Add option -i to prioritize test runs by source file modification time and
previous failure state.

This optimal scheduling reduces typical test-and-fix iteration times to a
matter of seconds by rapidly answering the questions:

  1) Did my recent change fix tests that were previously failing?
  2) Do the tests I just wrote / modified still work?

The current implementation requires write permissions to the source tree
because it uses mtimes to track failures.

llvm-svn: 198150

llvm-svn: 198013

Since r197684, "install/bin/llvm-config --obj-root" hasn't shown the build tree. The builder was finding utils in the build tree, from the installed tree.

I will revert this after dragonegg builder would be tweaked not to use installed llvm-config.

llvm-svn: 197786

That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768

Unfortunately, the PowerPC instruction definitions make heavy use of the
positional operand encoding heuristic to map operands onto bitfield variables
in the instruction definitions. Changing this to use name-based mapping is not
trivial, however, because additional infrastructure needs to be designed to
handle mapping of complex operands (with multiple suboperands) onto multiple
bitfield variables.

In the mean time, this adds support for positionally encoded operands to
FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC
backend. To prevent an accidental reliance on this feature, and to prevent an
undesirable interaction with existing disassemblers, a backend must opt-in to
this support by setting the new decodePositionallyEncodedOperands
instruction-set bit to true.

When enabled, this iterates the variables that contribute to the instruction
encoding, just as the encoder does, and emulates the procedure the encoder uses
to map "numbered" operands to variables. The bit range for each variable is
also determined as the encoder determines them. This map is then consulted
during the decoder-generator's loop over operands to decode, allowing the
decoder to understand both position-based and name-based operand-to-variable
mappings.

As noted in the comment on the decodePositionallyEncodedOperands definition,
this support should be removed once it is no longer needed. There should be no
change to existing disassemblers.

llvm-svn: 197691

This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter
should recognize PointerLikeRegClass operands as register types, and generate
register-like decoding calls instead of treating them like immediates.

llvm-svn: 197680

The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

llvm-svn: 197532

llvm-svn: 197462

I was testing a stale bin/llvm-lit, which now lives at bin/llvm-lit.py
on Windows.

llvm-svn: 197446

This missing parameter was causing bin/llvm-lit to run the unittests
from my primary build directory instead of my self-hosting build
directory because llvm-config was on my PATH.

This more closely matches what 'make check' will pass to lit.py.

llvm-svn: 197444

Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384

Both FileCheck and clang's -verify need to escape strings for regexes,
so let's expose this as a utility in the Regex class.

llvm-svn: 197096

This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

llvm-svn: 196471

utils/llvm-lit: Generate "llvm-lit.py" rather than "llvm-lit" on Win32 hosts to let llvm-lit.py --use-processes work.

llvm-lit needs suffix.py for multiprocess to find a main module.

llvm-svn: 196328

llvm-svn: 196227

llvm-svn: 196066

llvm-svn: 195567