postfixing it with a number.

llvm-svn: 54468

r53941 (but this was not noticed due to the lack of a basic test for
SRETPromotion). 

llvm-svn: 54467

llvm-svn: 54464

llvm-svn: 54461

llvm-svn: 54460

llvm-svn: 54459

llvm-svn: 54458

llvm-svn: 54457

llvm-svn: 54456

llvm-svn: 54455

llvm-svn: 54454

llvm-svn: 54453

llvm-svn: 54452

llvm-svn: 54451

llvm-svn: 54450

llvm-svn: 54449

llvm-svn: 54448

llvm-svn: 54446

LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444

are allocated in the same buffer as the code,
jump tables, etc.

The default JIT memory manager does not handle buffer
overflow well.  I didn't introduce this and I'm not
attempting to fix it here, but it is more likely to
be hit now since we're putting more stuff in the
buffer.  This affects one test that I know of so far,
MultiSource/Benchmarks/NPB-serial/is.

llvm-svn: 54442

Factor code that finalize PHI nodes, jump tables, etc. out of SelectBasicBlock. No functionality changes.

llvm-svn: 54438

SDISel's constant branch folding can fold away self-loops, which doesn't result in any dead blocks, but
rather an incorrect phi input.  Add code to UnreachableMachineBlockElim to get rid of these entries.

llvm-svn: 54432

Correct handle cases where two phis are coalesced together, and correct break up the case where two different
phis want to coalesce with the same vreg.

llvm-svn: 54426

llvm-svn: 54425

llvm-svn: 54422

llvm-svn: 54421

llvm-svn: 54420

this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.

llvm-svn: 54418

when it meant to be emitting undef indices.

llvm-svn: 54417

Fix PR2355: bug in ChangeCompareStride. When the loop termination compare is the only use of its iv stride, the stride can be eliminated by moving it to another stride. If the scale is negative, swap the predicate instead of using a inverse predicate.

llvm-svn: 54415

llvm-svn: 54411

llvm-svn: 54408

Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.

llvm-svn: 54403

matters, the result is undefined anyway.

llvm-svn: 54396

tracking down that this was breaking llvm-gcc bootstrap on Linux.

llvm-svn: 54394

warning. There wasn't actually a problem here, because the contents of
the string are known.

llvm-svn: 54385

instead of having it call getIterationCount again.

llvm-svn: 54380

llvm-svn: 54378

llvm-svn: 54376

llvm-svn: 54375