No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199749

No functional change since the InstrItinData's were duplicated

llvm-svn: 199497

IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199495

[mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class as their non-microMIPS counterparts.

No functional change since both classes have the same InstrItinData definition.

llvm-svn: 199402

No functional change since there are no InstrItinData's.

llvm-svn: 199396

IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.

llvm-svn: 199391

This matches the itin class used by the non-microMIPS equivalents of these
instructions.

llvm-svn: 199389

llvm-svn: 199316

llvm-svn: 199315

llvm-svn: 198010

llvm-svn: 197696

llvm-svn: 197692

No functionality change.

llvm-svn: 195896

llvm-svn: 194569

llvm-svn: 194205

llvm-svn: 193992

llvm-svn: 193623

accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119

llvm-svn: 190745

llvm-svn: 190744

into a 5-bit or 6-bit field.

llvm-svn: 190226

This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.

llvm-svn: 190154

This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.

llvm-svn: 190152

This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.

llvm-svn: 190148

llvm-svn: 190144

load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830

assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824

llvm-svn: 188341

This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312

llvm-svn: 187832

unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821

No functionality change.

llvm-svn: 187468

llvm-svn: 182047

Patch by Zoran Jovanovic.

llvm-svn: 180241

Patch by Zoran Jovanovic.

llvm-svn: 180238

This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873