When a function has FP, the register scavenging spill slot offset already
was calculated.

llvm-svn: 37371

llvm-svn: 37365

llvm-svn: 37362

llvm-svn: 37355

matter until my last change).  Reenable tail merging by default.

llvm-svn: 37354

llvm-svn: 37353

If there is an empty block between a source and its successor block, it still requires a unconditional branch.

llvm-svn: 37344

llvm-svn: 37341

llvm-svn: 37331

llvm-svn: 37330

llvm-svn: 37328

only one successor.

llvm-svn: 37324

Temporarily, this breaks CodeGen/Generic/2006-02-12-InsertLibraryCall.ll
by exposing an unrelated latent problem; working on that.

llvm-svn: 37323

llvm-svn: 37321

llvm-svn: 37320

Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.

llvm-svn: 37318

When considering blocks with more than 2 predecessors, merge the block with
the largest number of matching insns, rather than the first block found.
Considering that 1 matching insn is enough to show a win for candidates that
already end with a branch.

llvm-svn: 37315

Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439

llvm-svn: 37311

llvm-svn: 37310

llvm-svn: 37309

llvm-svn: 37289

llvm-svn: 37288

for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285

llvm-svn: 37270

it occurs for multiple landing pads.

llvm-svn: 37267

llvm-svn: 37249

this case, the xform introduces an extra operation).  This compiles
PowerPC/compare-duplicate.ll into:

_test:
        subf r2, r3, r4
        cmplw cr0, r2, r3
        bne cr0, LBB1_2 ;F

instead of:

_test:
        slwi r2, r3, 1
        subf r3, r3, r4
        cmplw cr0, r4, r2
        bne cr0, LBB1_2 ;F

This is target independent of course.

llvm-svn: 37246

llvm-svn: 37237

llvm-svn: 37236

llvm-svn: 37235

llvm-svn: 37233

llvm-svn: 37231

llvm-svn: 37230

llvm-svn: 37227

llvm-svn: 37200

llvm-svn: 37198

llvm-svn: 37195

llvm-svn: 37190

i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169

add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets

llvm-svn: 37168