llvm-svn: 104705

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

llvm-svn: 104699

llvm-svn: 104697

llvm-svn: 104696

llvm-svn: 104692

llvm-svn: 104691

llvm-svn: 104689

llvm-svn: 104670

Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667

llvm-svn: 104664

llvm-svn: 104661

This reverts commit 104654.

llvm-svn: 104660

base class, since all the implementations are the same.

llvm-svn: 104659

llvm-svn: 104657

machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653

Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652

llvm-svn: 104651

llvm-svn: 104650

This is used to track variable information.

llvm-svn: 104649

llvm-svn: 104648

llvm-svn: 104646

llvm-svn: 104645

llvm-svn: 104644

as well.

llvm-svn: 104642

If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:

1:  y = g;
    x = sigsetjmp(env, 0);
    switch (x) {
    case 1:
      /* ... */
      goto run;  
    case 0:
  run:
      do_run(); /* marked as "no return" */
      break;
    case 3:
      if (...) {
        /* ... */
        goto run;
      }
      /* ... */
      break;
    }

2:  g = y;

"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).

The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.

llvm-svn: 104640

and testcases accordingly.

llvm-svn: 104635

are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634

llvm-svn: 104629

llvm-svn: 104628

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627

llvm-svn: 104626

Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624

llvm-svn: 104622

for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621

(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619

Fixes rdar://8017638

llvm-svn: 104617

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615