{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693

ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684

should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676

llvm-svn: 89672

llvm-svn: 89618

llvm-svn: 89576

Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison.

llvm-svn: 89574

llvm-svn: 89573

llvm-svn: 89572

llvm-svn: 89571

isn't necessary.

llvm-svn: 89568

backtraces.

llvm-svn: 89562

Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.

llvm-svn: 89542

llvm-svn: 89536

Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.

llvm-svn: 89516

llvm-svn: 89509

llvm-svn: 89507

and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506

Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500

(PPC specific).

llvm-svn: 89496

broke the Clang testsuite.

llvm-svn: 89495

Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491

llvm-svn: 89478

constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473

llvm-svn: 89443

llvm-svn: 89440

Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.

llvm-svn: 89423

llvm-svn: 89414

assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403

llvm-svn: 89396

$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G    lib/CodeGen/AsmPrinter/DwarfException.cpp
G    lib/Target/TargetLoweringObjectFile.cpp

llvm-svn: 89379

fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377

llvm-svn: 89369

llvm-svn: 89360

llvm-svn: 89337

llvm-svn: 89328

llvm-svn: 89326

llvm-svn: 89325

- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322

llvm-svn: 89316