for the number of bytes in a particular instruction
to using
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
   Desc.getSize()

This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.

llvm-svn: 165171

  * Return correct size and alignment for common symbols.

llvm-svn: 165170

<rdar://problem/12408181> Fixing a bug where we would try to look for types in a module, and then fail to look for them anywhere else because the same SymbolContext was being passed everywhere

llvm-svn: 165169

llvm-svn: 165168

llvm-svn: 165167

llvm-svn: 165166

In order to avoid rev-lock with Clang when moving to the new API, also
preserve the current API temporarily and insert a shim to implement the
new API in terms of the old.

llvm-svn: 165165

llvm-svn: 165164

llvm-svn: 165163

llvm-svn: 165162

llvm-svn: 165161

imports via ImportDecls.

llvm-svn: 165160

--- Reverse-merging r164909 into '.':
U    make/platform/clang_darwin.mk

llvm-svn: 165159

llvm-svn: 165158

Str may be smaller than Start->Name here. Use strncmp to avoid scanning past the
end. Found by valgrind.

llvm-svn: 165157

false is used as a baseline here, we may want to allow contraction in some of
the cases.  Found by valgrind.

llvm-svn: 165156

llvm-svn: 165151

llvm-svn: 165150

This parameter is useless because nowhere used explicitly and always
gets its default value - "false".

The patch reviewed by Rafael Espindola.

llvm-svn: 165149

multiple stores with a single load. We create the wide loads and stores (and their chains)
before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge
loads with a different chain. When that happened, the assumption that it is safe to RAUW
broke and a cycle was introduced.

llvm-svn: 165148

llvm-svn: 165147

llvm-svn: 165144

Most of the pieces for this were already in place, but a proper EmitVAArg
is needed for aggregates and complex numbers to be handled.  Although the
va_list for 64-bit PowerPC SVR4 consists of GPRs 3 through 10 together with
the overflow portion of the parameter save area, we can treat va_list as
pointing to contiguous memory for all parameters, since the back end forces
the parameter GPRs to memory for varargs functions.

There is no need at this time to model parameters and return values beyond
what the DefaultABIInfo provides.

llvm-svn: 165143

llvm-svn: 165142

llvm-svn: 165141

Don't call getAsUnsignedInteger directly, it fails to compile if uint64_t is not "unsigned long long".

while there add more test cases.

llvm-svn: 165140

which is neither correct nor necessary. The use of this routine was
eliminated by r165137.

llvm-svn: 165139

llvm-svn: 165138

the ASTReader doesn't attach a body to a function that is already
defined elsewhere.

llvm-svn: 165137

llvm-svn: 165136

llvm-svn: 165135

llvm-svn: 165134

that doesn't have a 'self' as this implicitly captures 'self' and could
create retain cycles. Provide fixit. // rdar://11194874

llvm-svn: 165133

enums. This allows for better encapsulation of the Attributes class.

llvm-svn: 165132

1. Add mipsel-linux-android to the list of valid MIPS target triples.
2. Add <gcc install path>/mips-r2 to the list of toolchain specific path
   prefixes if target is mipsel-linux-android.

The patch reviewed by Logan Chien.

llvm-svn: 165131

and by specifying a target.

llvm-svn: 165130

fast div/rem instruction (for Intel Atom).

Test case for llvm commit 165126.

Patch by Tyler Nowicki.

llvm-svn: 165129

Patch by Amara Emerson.

llvm-svn: 165128

instruction (for Intel Atom) was not being done by Clang, because
the type context used by Clang is not the default context.

It fixes the problem by getting the global context types for each div/rem
instruction in order to compare them against the types in the BypassTypeMap.

Tests for this will be done as a separate patch to Clang.

Patch by Tyler Nowicki.

llvm-svn: 165126

is not profitable in many cases because modern processors perform multiple stores
in parallel and merging stores prior to merging requires extra work. We handle two main cases:

1. Store of multiple consecutive constants:
  q->a = 3;
  q->4 = 5;
In this case we store a single legal wide integer.

2. Store of multiple consecutive loads:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;
In this case we load/store either ilegal vector registers or legal wide integer registers.

llvm-svn: 165125