- Mar 28, 2012
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Akira Hatanaka authored
imposes a constraint that GOT16 referring to a local symbol or HI16 has to be followed immediately by a matching LO16 relocation. llvm-svn: 153553
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Akira Hatanaka authored
them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
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Akira Hatanaka authored
any side effects. llvm-svn: 153551
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Benjamin Kramer authored
llvm-svn: 153543
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Benjamin Kramer authored
llvm-svn: 153542
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- Mar 27, 2012
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Akira Hatanaka authored
llvm-svn: 153536
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Akira Hatanaka authored
If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the beginning and end of a function. llvm-svn: 153528
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Jakob Stoklund Olesen authored
This pass tries to update kill flags, but there are still many bugs. Passes after the load/store optimizer don't need accurate liveness, so don't even try. <rdar://problem/11101911> llvm-svn: 153519
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Jakob Stoklund Olesen authored
llvm-svn: 153516
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Craig Topper authored
llvm-svn: 153502
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Craig Topper authored
llvm-svn: 153500
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Akira Hatanaka authored
MachinePointerInfo when getStore is called to create a node that stores an argument passed in register to the stack. Without this change, the post RA scheduler will fail to discover the dependencies between the stores instructions and the instructions that load from a structure passed by value. The link to the related discussion is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html llvm-svn: 153499
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Akira Hatanaka authored
llvm-svn: 153498
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Akira Hatanaka authored
llvm-svn: 153497
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Akira Hatanaka authored
set it in MipsMCCodeEmitter::getMachineOpValue. Assert in getMachineOpValue if MachineOperand MO is of an unexpected type. llvm-svn: 153494
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Akira Hatanaka authored
offset applied to it. llvm-svn: 153493
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Akira Hatanaka authored
cleared. No functionality change. llvm-svn: 153491
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Akira Hatanaka authored
llvm-svn: 153486
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Evan Cheng authored
produces a 32-bit immediate which is consumed by the use. It tries to fold the immediate by breaking it into two parts and fold them into the immmediate fields of two uses. e.g movw r2, #40885 movt r3, #46540 add r0, r0, r3 => add.w r0, r0, #3019898880 add.w r0, r0, #30146560 ; However, this transformation is incorrect if the user produces a flag. e.g. movw r2, #40885 movt r3, #46540 adds r0, r0, r3 => add.w r0, r0, #3019898880 adds.w r0, r0, #30146560 Note the adds.w may not set the carry flag even if the original sequence would. rdar://11116189 llvm-svn: 153484
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- Mar 26, 2012
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Craig Topper authored
llvm-svn: 153429
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Craig Topper authored
llvm-svn: 153422
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Craig Topper authored
llvm-svn: 153421
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- Mar 25, 2012
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Craig Topper authored
llvm-svn: 153415
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- Mar 24, 2012
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Hal Finkel authored
The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that are smaller than 64 bits be zero extended to 64 bits. llvm-svn: 153373
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Justin Holewinski authored
Code such as: %vreg100 = setcc %vreg10, -1, SETNE brcond %vreg10, %tgt was being incorrectly morphed into %vreg100 = and %vreg10, 1 brcond %vreg10, %tgt where the 'and' instruction could be eliminated since such logic is on 1-bit types in the PTX back-end, leaving us with just: brcond %vreg10, %tgt which essentially gives us inverted branch conditions. llvm-svn: 153364
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Jim Grosbach authored
No functional change, just tidy up the code and nomenclature a bit. llvm-svn: 153347
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- Mar 23, 2012
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Benjamin Kramer authored
llvm-svn: 153328
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Benjamin Kramer authored
New code should use raw_ostream. llvm-svn: 153326
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Eric Christopher authored
llvm-svn: 153307
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- Mar 22, 2012
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Silviu Baranga authored
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. llvm-svn: 153252
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Silviu Baranga authored
llvm-svn: 153251
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Silviu Baranga authored
llvm-svn: 153250
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Craig Topper authored
llvm-svn: 153245
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Hal Finkel authored
I don't have a small test case yet, but I'll try to construct one. llvm-svn: 153240
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- Mar 21, 2012
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Kevin Enderby authored
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp . llvm-svn: 153218
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Joerg Sonnenberger authored
llvm-svn: 153185
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Benjamin Kramer authored
llvm-svn: 153184
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Joerg Sonnenberger authored
the invalid cases. At least 16bit operand in 64bit mode is currently not rejected in the parser. llvm-svn: 153166
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Craig Topper authored
llvm-svn: 153155
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Craig Topper authored
Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend. llvm-svn: 153154
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