"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969

llvm-svn: 148964

Thanks to Eli for noticing.

llvm-svn: 148947

llvm-svn: 148946

savings from a pointer argument becoming an alloca. Sometimes callees will even
compare a pointer to null and then branch to an otherwise unreachable block!
Detect these cases and compute the number of saved instructions, instead of
bailing out and reporting no savings.

llvm-svn: 148941

llvm-svn: 148934

Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.

llvm-svn: 148933

helper method for the common operation of extracting an element
out of a constant aggregate.

llvm-svn: 148931

llvm-svn: 148929

Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.

llvm-svn: 148927

"Introduce a new ConstantVector::getSplat constructor function to 
simplify a really common case."

llvm-svn: 148924

llvm-svn: 148922

 

llvm-svn: 148918

- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917

expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916

Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.

llvm-svn: 148914

inttypes.h is not supplied in msvc.

llvm-svn: 148912

in asserts.

llvm-svn: 148910

llvm-svn: 148909

Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908

Original log:
    Introduce a new ConstantVector::getSplat constructor function to
    simplify a really common case.

llvm-svn: 148906

simplify a really common case.

llvm-svn: 148901

load an immediate. 

llvm-svn: 148900

did something extremely surprising, and shadowed actually useful 
implementations that had completely different behavior.

llvm-svn: 148898

llvm-svn: 148897

llvm-svn: 148884

llvm-svn: 148883

llvm-svn: 148882

A REG_SEQUENCE instruction is lowered into a sequence of partial defs:

  %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
  %vreg7:ssub_1<def> = COPY %vreg2
  %vreg7:ssub_2<def> = COPY %vreg2
  %vreg7:ssub_3<def> = COPY %vreg2

The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write.  Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.

This fixes PR11841.

llvm-svn: 148879

llvm-svn: 148878

which is what N32/64 does.

llvm-svn: 148875

llvm-svn: 148871

llvm-svn: 148869

When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.

llvm-svn: 148865

llvm-svn: 148864

llvm-svn: 148862

llvm-svn: 148849

llvm-svn: 148846

llvm-svn: 148836

Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.

llvm-svn: 148833