-relocation-model=static.

llvm-svn: 146432

llvm-svn: 145912

registers.

llvm-svn: 144017

llvm-svn: 141694

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

llvm-svn: 141613

llvm-svn: 141476

registers.

llvm-svn: 141019

It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735

multiclasses.

llvm-svn: 140731

These are strictly utilities for registering targets and components.

llvm-svn: 138450

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

llvm-svn: 134661

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 134244

llvm-svn: 134224

llvm-svn: 134030

llvm-svn: 134024

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

llvm-svn: 128718

llvm-svn: 128650

llvm-svn: 127003

llvm-svn: 108567

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099

llvm-svn: 108066

llvm-svn: 108063

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121

llvm-svn: 100214

folder to be tolerant of debug info following the
branch(es) at the end of a block.

llvm-svn: 100168

llvm-svn: 93876

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

llvm-svn: 89821

because the testcase is triggering one more bug.

llvm-svn: 88674