- Aug 03, 2009
-
-
Jakob Stoklund Olesen authored
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG instriction because it is an identity copy, make sure that the same registers are alive before and after the elimination. When the super-register is marked <undef> this requires inserting an IMPLICIT_DEF instruction to make sure the super register is live. Fix a related bug where a kill flag on the inserted sub-register was not transferred properly. Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid. llvm-svn: 77989
-
Jakob Stoklund Olesen authored
Thanks Chris. llvm-svn: 77987
-
Eli Friedman authored
appropriate. Patch per report on llvmdev. No testcase because the original report didn't come with a testcase, and I can't come up with a case that actually fails. llvm-svn: 77986
-
Chris Lattner authored
llvm-svn: 77984
-
Chris Lattner authored
code that I will be using shortly. llvm-svn: 77983
-
Bob Wilson authored
llvm-svn: 77982
-
Evan Cheng authored
llvm-svn: 77978
-
Chris Lattner authored
This will cause it to enter the ".text" section instead of "_text" but masm is already broken. llvm-svn: 77977
-
Chris Lattner authored
llvm-svn: 77976
-
Daniel Dunbar authored
- The theory is these should never actually be called, since these boil down to passes which can access the target data via the standard mechanism. llvm-svn: 77975
-
Sanjiv Gupta authored
llvm-svn: 77974
-
Benjamin Kramer authored
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:". llvm-svn: 77971
-
Anton Korobeynikov authored
Since we're generating stubs by hands we don't follow the ABI and don't create a register spill area. Don't use this area in compilation callback! llvm-svn: 77968
-
Evan Cheng authored
Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. llvm-svn: 77967
-
Anton Korobeynikov authored
llvm-svn: 77966
-
Anton Korobeynikov authored
llvm-svn: 77965
-
Anton Korobeynikov authored
Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64). llvm-svn: 77964
-
Anton Korobeynikov authored
Cleanup Darwin MMX calling conv stuff - make the stuff more generic. This also fixes a subtle bug, when 6th v1i64 argument passed wrongly. llvm-svn: 77963
-
Anton Korobeynikov authored
Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. llvm-svn: 77962
-
Devang Patel authored
llvm-svn: 77959
-
Rafael Espindola authored
llvm-svn: 77956
-
Daniel Dunbar authored
llvm-svn: 77953
-
Daniel Dunbar authored
llvm-svn: 77950
-
Evan Cheng authored
llvm-svn: 77949
-
Daniel Dunbar authored
This is not just a matter of passing in the target triple from the module; currently backends are making decisions based on the build and host architecture. The goal is to migrate to making these decisions based off of the triple (in conjunction with the feature string). Thus most clients pass in the target triple, or the host triple if that is empty. This has one important change in the way behavior of the JIT and llc. For the JIT, it was previously selecting the Target based on the host (naturally), but it was setting the target machine features based on the triple from the module. Now it is setting the target machine features based on the triple of the host. For LLC, -march was previously only used to select the target, the target machine features were initialized from the module's triple (which may have been empty). Now the target triple is taken from the module, or the host's triple is used if that is empty. Then the triple is adjusted to match -march. The take away is that -march for llc is now used in conjunction with the host triple to initialize the subtarget. If users want more deterministic behavior from llc, they should use -mtriple, or set the triple in the input module. llvm-svn: 77946
-
Rafael Espindola authored
llvm-svn: 77944
-
Rafael Espindola authored
Thanks to Eli Friedman for noticing it. llvm-svn: 77942
-
Rafael Espindola authored
Fixes PR4669 llvm-svn: 77940
-
Evan Cheng authored
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. llvm-svn: 77939
-
Eli Friedman authored
options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. llvm-svn: 77938
-
Andreas Bolka authored
llvm-svn: 77932
-
Daniel Dunbar authored
llvm-svn: 77931
-
Bill Wendling authored
- Tidy up some headers. llvm-svn: 77929
-
Daniel Dunbar authored
- The C, C++, MSIL, and Mips backends still need the module. llvm-svn: 77927
-
Richard Osborne authored
llvm-svn: 77920
-
Bill Wendling authored
pushes in the function prolog if the function doesn't have any stack space, i.e. for a prolog like: 0x40011870: push %r15 0x40011872: push %r14 0x40011874: push %rbx Patch by Zoltan! llvm-svn: 77919
-
Daniel Dunbar authored
Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
-
- Aug 02, 2009
-
-
Jakob Stoklund Olesen authored
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end. __builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load. We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds. llvm-svn: 77917
-
Nick Lewycky authored
llvm-svn: 77914
-
Daniel Dunbar authored
llvm-svn: 77913
-