around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791

builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

llvm-svn: 107758

The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

llvm-svn: 107529

list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

llvm-svn: 107520

llvm-svn: 107212

llvm-svn: 107112

llvm-svn: 106834

names for the array fields.

llvm-svn: 106803

llvm-svn: 106795

the array fields in these structs.

llvm-svn: 106794

llvm-svn: 106671

Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.

llvm-svn: 106670

Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey!

llvm-svn: 106620

later on. But we need them saved in the symbols directory.

llvm-svn: 106604

a toplevel 'defm', make sure to properly resolve references.

llvm-svn: 106570

llvm-svn: 106470

Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work.

llvm-svn: 106406

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

llvm-svn: 106305

MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296

llvm-svn: 106246

llvm-svn: 106207

llvm-svn: 106201

be evaluated for 'bit' operators

llvm-svn: 106185

llvm-svn: 106179

llvm-svn: 106178

The attribute class generation support is still somewhat limited.
See the accompanying clang commit for more details.

llvm-svn: 106174

llvm-svn: 106171

llvm-svn: 106054

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

llvm-svn: 105970

Radar 7894069.

llvm-svn: 105938

llvm-svn: 105929

Add code for generating bits of semachecking

llvm-svn: 105907

llvm-svn: 105888

warnings, and don't shift by a bool.  Patch by Rizky Herucakra!

llvm-svn: 105886

llvm-svn: 105874

Introduce the VEX_X field

llvm-svn: 105859

llvm-svn: 105858

quoting problems. Not particularly ideal, but should work ok. Based on a patch by
Michael Spencer!

llvm-svn: 105855