Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086

llvm-svn: 131085

"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

llvm-svn: 131070

Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.

llvm-svn: 131059

Patch by Stephen Hines.

llvm-svn: 131045

2. Remove unused function.
3. Correct indentation.

llvm-svn: 131028

llvm-svn: 131012

llvm-svn: 130984

Patch by Wei-Ren Chen

llvm-svn: 130980

llvm-svn: 130951

No test because I can't think of any way to write one that won't break quickly.

llvm-svn: 130932

who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>

llvm-svn: 130918

It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.

llvm-svn: 130892

llvm-svn: 130857

llvm-svn: 130854

llvm-svn: 130850

Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.

llvm-svn: 130847

coalescing.

llvm-svn: 130814

LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

llvm-svn: 130801

<rdar://problem/8460511>

llvm-svn: 130791

llvm-svn: 130774

llvm-svn: 130766

it's possible.

llvm-svn: 130764

llvm-svn: 130763

llvm-svn: 130755

llvm-svn: 130749

string template.

Fixes rdar://8493866

llvm-svn: 130747

model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743

llvm-svn: 130716

llvm-svn: 130693

llvm-svn: 130691

llvm-svn: 130690

llvm-svn: 130658

likely a result of copy/paste.

llvm-svn: 130640

-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637

llvm-svn: 130635

for all symbol differences and can drop the old EmitPCRelSymbolValue
method.

This also make getExprForFDESymbol on ELF equal to the one on MachO, and it
can be made non-virtual.

llvm-svn: 130634

less agressive about disabling cfi on linux :-(

llvm-svn: 130626

after folding ADD32ri to ADD32mi, so don't do that.

This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:

16L             %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L             %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9

That should never happen, the live range should be split instead.

llvm-svn: 130625

Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

llvm-svn: 130623