- Jul 13, 2012
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Jack Carter authored
is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. llvm-svn: 160183
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Benjamin Kramer authored
llvm-svn: 160173
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Craig Topper authored
llvm-svn: 160162
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- Jul 12, 2012
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Benjamin Kramer authored
Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. llvm-svn: 160137
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Benjamin Kramer authored
The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
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Craig Topper authored
llvm-svn: 160110
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Manman Ren authored
llvm-svn: 160093
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Manman Ren authored
It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. llvm-svn: 160090
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Jack Carter authored
When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. llvm-svn: 160084
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- Jul 11, 2012
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Jack Carter authored
Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. llvm-svn: 160081
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Akira Hatanaka authored
order of binary encoding. Patch by Vladimir Medic. llvm-svn: 160073
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Chad Rosier authored
comments. llvm-svn: 160069
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Manman Ren authored
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. llvm-svn: 160066
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Akira Hatanaka authored
llvm-svn: 160064
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Chad Rosier authored
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. llvm-svn: 160055
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Nadav Rotem authored
When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers. llvm-svn: 160044
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Akira Hatanaka authored
Patch by Sasa Stankovic. llvm-svn: 160031
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Jack Carter authored
Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. llvm-svn: 160028
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- Jul 10, 2012
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Chad Rosier authored
X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. llvm-svn: 160009
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Chad Rosier authored
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 llvm-svn: 160002
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Nadav Rotem authored
Improve the loading of load-anyext vectors by allowing the codegen to load multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. llvm-svn: 159991
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Richard Barton authored
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! llvm-svn: 159989
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Craig Topper authored
llvm-svn: 159983
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Jim Grosbach authored
Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. llvm-svn: 159974
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Akira Hatanaka authored
llvm-svn: 159971
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- Jul 09, 2012
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Chad Rosier authored
llvm-svn: 159960
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Manman Ren authored
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. llvm-svn: 159955
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Akira Hatanaka authored
Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
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Richard Barton authored
llvm-svn: 159948
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Richard Barton authored
llvm-svn: 159945
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Richard Barton authored
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) llvm-svn: 159938
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Richard Barton authored
llvm-svn: 159937
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Richard Barton authored
llvm-svn: 159936
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Richard Barton authored
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable. llvm-svn: 159935
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- Jul 07, 2012
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Andrew Trick authored
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
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Manman Ren authored
It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. llvm-svn: 159888
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Chad Rosier authored
should be camel case, and start with a lower case letter. llvm-svn: 159877
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- Jul 06, 2012
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Jim Grosbach authored
llvm-svn: 159864
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Akira Hatanaka authored
llvm-svn: 159854
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Akira Hatanaka authored
Include file MipsGenRegisterInfo.inc. llvm-svn: 159851
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