llvm-svn: 157493

llvm-svn: 157492

to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479

llvm-svn: 157446

llvm-svn: 157433

This back-end was deprecated in favor of the NVPTX back-end.

NV_CONTRIB

llvm-svn: 157417

Expand test case for this.

Patch by Reed Kotler.

llvm-svn: 157410

First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408

llvm-svn: 157380

llvm-svn: 157375

llvm-svn: 157374

Make some opcode tables static and const. Allows code to avoid making copies to pass the tables around.

llvm-svn: 157373

llvm-svn: 157369

llvm-svn: 157368

Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.

llvm-svn: 157367

llvm-svn: 157358

Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157336

llvm-svn: 157313

llvm-svn: 157309

llvm-svn: 157292

Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908.

llvm-svn: 157236

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221

t2RSB defined the operand correctly, but tRSBS didn't.

llvm-svn: 157200

Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.

llvm-svn: 157175

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.

llvm-svn: 157159

llvm-svn: 157152

They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151

The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133

llvm-svn: 157129

llvm-svn: 157127

llvm-svn: 157122

llvm-svn: 157112

llvm-svn: 157109

Patch by Jack Carter.

llvm-svn: 157093

Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062

Patch by Jack Carter.

llvm-svn: 157057

llvm-svn: 157044

llvm-svn: 157043