llvm-svn: 138660

llvm-svn: 138657

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons.  We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts.  Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits.  This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

llvm-svn: 138642

This should fix PR10772.

llvm-svn: 138636

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions.  This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

llvm-svn: 138630

Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625

llvm-svn: 138623

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621

llvm-svn: 138592

llvm-svn: 138589

llvm-svn: 138588

llvm-svn: 138587

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568

llvm-svn: 138566

llvm-svn: 138562

Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.

llvm-svn: 138553

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138546

llvm-svn: 138545

llvm-svn: 138540

llvm-svn: 138536

llvm-svn: 138534

file, and move more code around!

llvm-svn: 138521

llvm-svn: 138520

llvm-svn: 138519

the missing ones for AVX.

llvm-svn: 138518

llvm-svn: 138517

pattern for 128-bit AVX mode.

llvm-svn: 138516

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!

llvm-svn: 138515

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!

llvm-svn: 138514

Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.

llvm-svn: 138507

Hook up 64-bit atomic load/store on x86-32.  I plan to write more efficient implementations eventually.

llvm-svn: 138505

llvm-svn: 138501

We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

llvm-svn: 138500

Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494

llvm-svn: 138492

Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488