llvm-svn: 26272

llvm-svn: 26271

exactly the API we wanted to call into.  This fixes the crash on crafty last
night.

llvm-svn: 26269

llvm-svn: 26268

llvm-svn: 26267

llvm-svn: 26266

llvm-svn: 26265

llvm-svn: 26264

Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal

llvm-svn: 26263

llvm-svn: 26262

generate illegal nodes.

llvm-svn: 26261

llvm-svn: 26260

llvm-svn: 26259

llvm-svn: 26258

llvm-svn: 26257

opcodes on ppc.

llvm-svn: 26256

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).

llvm-svn: 26254

llvm-svn: 26253

llvm-svn: 26252

llvm-svn: 26251

llvm-svn: 26250

llvm-svn: 26249

risk :)

llvm-svn: 26248

issue. Need to do more experiments.

llvm-svn: 26247

llvm-svn: 26246

llvm-svn: 26245

llvm-svn: 26244

other small targets that do that can be learned from.  They also have
the added advantage of being tested :)

llvm-svn: 26243

turns out not to point to a constant string but it forgot change the offset
back.

llvm-svn: 26242

   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241

llvm-svn: 26240

llvm-svn: 26239

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238

llvm-svn: 26237

llvm-svn: 26236

Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*.  Apparently they do different things :)

This fixes a testcase that nate reduced from spass.

Also included are a couple minor code changes that don't affect the generated
code at all.

llvm-svn: 26235

llvm-svn: 26234

distinguish between objects and register names, now we can have stuff
with names like "f84", "in6" etc etc.

this should fix one or two tests

llvm-svn: 26232

We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231