llvm-svn: 158471

being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470

llvm-svn: 158446

llvm-svn: 158445

llvm-svn: 158443

llvm-svn: 158437

llvm-svn: 158436

llvm-svn: 158434

llvm-svn: 158433

as a scratch register when they are expanded to long branches.

llvm-svn: 158432

to load an immediate that does not fit into 16-bit. 

llvm-svn: 158431

to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size. 

llvm-svn: 158430

compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.

llvm-svn: 158429

Long-branches need access to the global base register to get the destination
address.

llvm-svn: 158428

object for the global base register.

This is the first of a series of patches which implements long branch expansion
for MIPS.

llvm-svn: 158427

delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.

This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.

llvm-svn: 158426

pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419

llvm-svn: 158414

llvm-svn: 158413

llvm-svn: 158410

llvm-svn: 158409

llvm-svn: 158404

Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.

llvm-svn: 158396

llvm-svn: 158393

Patch by Reed Kotler.

llvm-svn: 158382

until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.

llvm-svn: 158381

non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions

Patch by Reed Kotler.

llvm-svn: 158378

llvm-svn: 158373

Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 158368

On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.

llvm-svn: 158366

POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).

Patch by Andreas Tobler.

llvm-svn: 158363

Original commit message:
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().

Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

llvm-svn: 158349

This commit broke most of the PowerPC unit tests when running on
Intel/Apple.

llvm-svn: 158345

Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).

llvm-svn: 158337

llvm-svn: 158324

The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.

No functionality change.

llvm-svn: 158323

llvm-svn: 158322

This is necessary on Linux and supported on Darwin, see PR2604.

llvm-svn: 158315

This functionality mirrors that available on PPC/Darwin.

llvm-svn: 158314

No functional change; these will be used by upcoming scheduler enhancements.

llvm-svn: 158313