Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.

llvm-svn: 40578

llvm-svn: 40572

llvm-svn: 40566

Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555

llvm-svn: 40547

llvm-svn: 40538

llvm-svn: 40537

llvm-svn: 40535

don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529

llvm-svn: 40528

llvm-svn: 40517

x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504

llvm-svn: 40502

llvm-svn: 40501

llvm-svn: 40499

AsmPrinter::doFinalization.

llvm-svn: 40487

 - Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481

llvm-svn: 40480

register instead of loading each element individually.

llvm-svn: 40478

Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472

llvm-svn: 40443

llvm-svn: 40441

    __builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411

llvm-svn: 40132

llvm-svn: 40123

code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076

llvm-svn: 40071

Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).

llvm-svn: 40070

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 40028

Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.

llvm-svn: 40018

and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015

llvm-svn: 39998

llvm-svn: 39984

llvm-svn: 39978

llvm-svn: 39977

Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.

llvm-svn: 39974

llvm-svn: 39967

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

llvm-svn: 39772