llvm-svn: 106677

llvm-svn: 106672

llvm-svn: 106671

branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.

llvm-svn: 106662

Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.

llvm-svn: 106634

to using that.

llvm-svn: 106633

MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

llvm-svn: 106631

llvm-svn: 106621

Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.

Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614

llvm-svn: 106600

testcases this time.

llvm-svn: 106593

llvm-svn: 106588

llvm-svn: 106586

Radar 8031193.

llvm-svn: 106582

llvm-svn: 106574

llvm-svn: 106557

llvm-svn: 106556

llvm-svn: 106542

llvm-svn: 106517

llvm-svn: 106513

but it will cover uses of blockaddress that are actually in a function.

llvm-svn: 106502

rolling our own.

llvm-svn: 106501

llvm-svn: 106500

llvm-svn: 106499

llvm-svn: 106486

Radar 8104310.

llvm-svn: 106484

being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483

llvm-svn: 106482

Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.

llvm-svn: 106481

llvm-svn: 106467

llvm-svn: 106466

llvm-svn: 106465

llvm-svn: 106457

llvm-svn: 106455

llvm-svn: 106448

llvm-svn: 106447

llvm-svn: 106446

llvm-svn: 106445

Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms

llvm-svn: 106437

Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed

llvm-svn: 106436