llvm-svn: 4828

.cpp to return the iterator correctly.

llvm-svn: 4827

llvm-svn: 4826

llvm-svn: 4825

llvm-svn: 4824

MO_MachineRegister, we no longer distinguish Virtual vs. Machine registers
externally, they're ALL registers, all equal.

Registers are only differentiated whether they are >=
MRegisterInfo::FirstVirtual or not.

llvm-svn: 4823

llvm-svn: 4822

llvm-svn: 4821

llvm-svn: 4820

llvm-svn: 4819

llvm-svn: 4818

llvm-svn: 4817

llvm-svn: 4816

llvm-svn: 4815

llvm-svn: 4814

llvm-svn: 4813

instructions.  Right now the only users are load instructions, and Misha's
spill code

llvm-svn: 4812

llvm-svn: 4811

llvm-svn: 4810

llvm-svn: 4809

llvm-svn: 4808

llvm-svn: 4807

llvm-svn: 4806

llvm-svn: 4805

llvm-svn: 4804

llvm-svn: 4803

llvm-svn: 4802

pass.  Detect and flag them.

llvm-svn: 4801

register versions

llvm-svn: 4800

llvm-svn: 4799

llvm-svn: 4798

llvm-svn: 4797

llvm-svn: 4796

Basically just adds OpSize flags for instructions that need them.

llvm-svn: 4795

llvm-svn: 4794

for example.

llvm-svn: 4793

doesn't assert fail. And everyone's happy. Yay!

llvm-svn: 4792

llvm-svn: 4791

llvm-svn: 4790

llvm-svn: 4789