Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233

llvm-svn: 113224

llvm-svn: 113200

teach LazyValueInfo to use them.

llvm-svn: 113196

Switch from isWeakForLinker to mayBeOverridden which is more accurate.

Add more statistics and debugging info. Add comments. Move static function
outside anonymous namespace.

llvm-svn: 113190

llvm-svn: 113189

llvm-svn: 113188

Fix zeroExtend and signExtend to support empty sets, and to return the smallest
possible result set which contains the extension of each element in their
inputs. For example zext i8 [100, 10) to i16 is now [0, 256), not i16 [100, 10)
which contains 63446 members.

llvm-svn: 113187

always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530

llvm-svn: 113186

llvm-svn: 113184

allowing unsigned 8-bit operands.  This fixes rdar://8208481

llvm-svn: 113182

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176

llvm-svn: 113167

failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).

llvm-svn: 113166

llvm-svn: 113165

into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163

llvm-svn: 113158

llvm-svn: 113157

llvm-svn: 113155

llvm-svn: 113147

llvm-svn: 113146

llvm-svn: 113144

llvm-svn: 113135

in the duplicated block instead of duplicating them.  

Duplicating them into the end of the loop and the preheader 
means that we got a phi node in the header of the loop, 
which prevented LICM from hoisting them.  GVN would
usually come around later and merge the duplicated 
instructions so we'd get reasonable output... except that
anything dependent on the shoulda-been-hoisted value can't
be hoisted.  In PR5319 (which this fixes), a memory value
didn't get promoted.

llvm-svn: 113134

Loop::hasLoopInvariantOperands method. Remove
a useless and confusing Loop::isLoopInvariant(Instruction)
method, which didn't do what you thought it did.

No functionality change.

llvm-svn: 113133

pattern, so there is no need to define a matching function.

llvm-svn: 113122

llvm-svn: 113119

llvm-svn: 113117

llvm-svn: 113116

llvm-svn: 113115

llvm-svn: 113114

llvm-svn: 113113

llvm-svn: 113109

llvm-svn: 113108

llvm-svn: 113106

This reduces malloc traffic (yay!) and removes MergeFunctionsEqualityInfo.

llvm-svn: 113105

strong functions first to make sure they're the canonical definitions and then
do a second pass looking only for weak functions.

llvm-svn: 113104

Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.

llvm-svn: 113102

Clobber ranges are no longer used when joining physical registers.
Instead, all aliases are checked for interference.

llvm-svn: 113084