llvm-svn: 78777

llvm-svn: 78776

Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761

llvm-svn: 78745

"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.

llvm-svn: 78737

llvm-svn: 78736

darwin/arm support for .no_dead_strip

llvm-svn: 78734

llvm-svn: 78732

llvm-svn: 78730

llvm-svn: 78729

template in PPC backend for TAI.

llvm-svn: 78727

llvm-svn: 78717

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

LLVMTargetMachine ctor.  It is currently unused.

llvm-svn: 78711

version.  This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.

The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.

llvm-svn: 78709

llvm-svn: 78701

llvm-svn: 78683

llvm-svn: 78678

llvm-svn: 78666

llvm-svn: 78665

llvm-svn: 78659

match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658

llvm-svn: 78657

llvm-svn: 78655

llvm-svn: 78654

the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646

llvm-svn: 78632

llvm-svn: 78629

llvm-svn: 78627

and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625

Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.

llvm-svn: 78622

node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615

llvm-svn: 78610

llvm-svn: 78604

llvm-svn: 78595

llvm-svn: 78594

llvm-svn: 78593

llvm-svn: 78576

per pointer.

llvm-svn: 78574

llvm-svn: 78573