llvm-svn: 26443

llvm-svn: 26441

implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

llvm-svn: 26440

llvm-svn: 26436

- All abstrct vector nodes must have # of elements and element type as their
first two operands.

llvm-svn: 26432

Add array of debug descriptor support.

llvm-svn: 26428

unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

llvm-svn: 26419

unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26417

llvm-svn: 26416

llvm-svn: 26410

llvm-svn: 26409

llvm-svn: 26404

llvm-svn: 26402

llvm-svn: 26401

llvm-svn: 26390

llvm-svn: 26381

llvm-svn: 26371

exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).

When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.

llvm-svn: 26369

Add a minor compile time win, no codegen change.

llvm-svn: 26368

This gets rid of two gotos, which is always nice, and also adds some comments.

No functionality change, this is just a refactor.

llvm-svn: 26367

llvm-svn: 26364

llvm-svn: 26362

Add support for addressing modes.

llvm-svn: 26361

llvm-svn: 26358

(to allow llvm-gcc4 to build.)

llvm-svn: 26355

llvm-svn: 26351

llvm-svn: 26350

llvm-svn: 26346

llvm-svn: 26339

to inline asms.  Mark some methods const.

llvm-svn: 26334

several bugs in inline asm expanded operands.

llvm-svn: 26332

llvm-svn: 26331

llvm-svn: 26328

llvm-svn: 26318

a single register number.  This fully implements promotion for inline asms,
expand is close but not quite right yet.

llvm-svn: 26316

llvm-svn: 26314

llvm-svn: 26308

llvm-svn: 26306

packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294

them to get ressurected, in which case, deleting the undead nodes is
unfriendly.

llvm-svn: 26291