llvm-svn: 107613

llvm-svn: 107610

v2f32 is illegal on x86.

llvm-svn: 107609

the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601

v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600

llvm-svn: 107599

llvm-svn: 107585

(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583

llvm-svn: 107560

llvm-svn: 107558

llvm-svn: 107552

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

llvm-svn: 107550

llvm-svn: 107549

llvm-svn: 107540

- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523

- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

llvm-svn: 107509

llvm-svn: 107448

llvm-svn: 107438

Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405

llvm-svn: 107404

llvm-svn: 107377

to SelectionDAG.

llvm-svn: 107376

llvm-svn: 107375

the same address.

llvm-svn: 107373

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

llvm-svn: 107308

llvm-svn: 107306

llvm-svn: 107300

llvm-svn: 107293

llvm-svn: 107280

llvm-svn: 107246

llvm-svn: 107245

llvm-svn: 107243

llvm-svn: 107241

llvm-svn: 107240

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

llvm-svn: 107225

llvm-svn: 107211

llvm-svn: 107206

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204