Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.

llvm-svn: 48542

attribute instead of ".protected".

llvm-svn: 48516

Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!

llvm-svn: 48515

in ppc64 mode.

llvm-svn: 48459

lowering over to SparcCallingConv.td.  We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.

llvm-svn: 48449

llvm-svn: 48448

llvm-svn: 48447

llvm-svn: 48445

other targets.  Use autogenerated calling conv to lower result of
calls.

llvm-svn: 48444

return lowering first.  This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.

llvm-svn: 48443

best practices.

llvm-svn: 48442

each lowering, which is 'best practice'.

llvm-svn: 48441

behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be.  Handle complex long long
and complex double (4 and 8 return regs).

llvm-svn: 48439

llvm-svn: 48438

llvm-svn: 48430

llvm-svn: 48422

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

llvm-svn: 48381

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

vectors go at the end of the memory area, after all
non-vector parameters.

llvm-svn: 48364

llvm-svn: 48361

Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).

llvm-svn: 48360

llvm-svn: 48359

llvm-svn: 48356

llvm-svn: 48346

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.

llvm-svn: 48310

1. There is now a "PAListPtr" class, which is a smart pointer around
   the underlying uniqued parameter attribute list object, and manages
   its refcount.  It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
   the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
   longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
   ParamAttrsWithIndex's, no need to make a SmallVector of a specific 
   size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
   dereferencing the pointer is simplified to just access the 
   PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
   bit simpler.

Phase #2 will rename some stuff (e.g. PAListPtr) and do other less 
invasive changes.

llvm-svn: 48289

X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.

llvm-svn: 48279

llvm-svn: 48269

llvm-svn: 48264

llvm-svn: 48257

that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256

works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243

llvm-svn: 48241

llvm-svn: 48240

llvm-svn: 48239

llvm-svn: 48224

llvm-svn: 48223

If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).

llvm-svn: 48220