make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998

No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994

This caused more offset errors.

llvm-svn: 145980

llvm-svn: 145976

1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971

ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970

llvm-svn: 145969

* Rename variables to reflect what they're actually used for.

llvm-svn: 145968

llvm-svn: 145961

llvm-svn: 145960

llvm-svn: 145954

llvm-svn: 145952

llvm-svn: 145947

llvm-svn: 145946

llvm-svn: 145929

Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.

llvm-svn: 145927

llvm-svn: 145926

Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.

llvm-svn: 145924

Same as r145922, just for ARM mode.

llvm-svn: 145923

Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922

Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.

llvm-svn: 145921

Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919

llvm-svn: 145912

llvm-svn: 145910

llvm-svn: 145896

llvm-svn: 145895

llvm-svn: 145894

rdar://10528060

llvm-svn: 145891

Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890

This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889

value over that much.

llvm-svn: 145888

rdar://10069056

llvm-svn: 145885

llvm-svn: 145883

Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881

Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871

llvm-svn: 145863

rdar://10529664

llvm-svn: 145860

PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853

them.

llvm-svn: 145852