llvm-svn: 35230

llvm-svn: 35205

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204

llvm-svn: 35152

llvm-svn: 35129

llvm-svn: 35125

llvm-svn: 35118

llvm-svn: 35108

llvm-svn: 35107

llvm-svn: 35105

llvm-svn: 35104

llvm-svn: 35097

llvm-svn: 35096

llvm-svn: 35095

 a legal target address immediate or scale.

llvm-svn: 35073

llvm-svn: 35070

the addition. Please let me know if you have suggestions.

llvm-svn: 35055

moves, loads, etc. are recognized.

llvm-svn: 35031

llvm-svn: 35026

llvm-svn: 35016

llvm-svn: 35009

zext/sext/aext stuff.

llvm-svn: 35008

load and stores.

llvm-svn: 35002

Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000

llvm-svn: 34978

from formal attributes' flags processing.

llvm-svn: 34963

llvm-svn: 34938

llvm-svn: 34905

llvm-svn: 34857

llvm-svn: 34849

passed in registers, not directly from the pregs themselves.

llvm-svn: 34838

llvm-svn: 34837

properly aligned

llvm-svn: 34788

llvm-svn: 34754

they always get registers.

llvm-svn: 34748

llvm-svn: 34739

llvm-svn: 34737

llvm-svn: 34734

llvm-svn: 34733

Factor out a CC_X86_32_Common convention, which is the part shared between
ccc, stdcall and fastcall

llvm-svn: 34732