llvm-svn: 135974

llvm-svn: 135826

InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812

llvm-svn: 135698

Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

llvm-svn: 135678

- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580

llvm-svn: 135550

llvm-svn: 135546

llvm-svn: 135537

llvm-svn: 135522

ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520

llvm-svn: 135514

llvm-svn: 135496

- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495

basic blocks.

llvm-svn: 135490

(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468

ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465

llvm-svn: 135464

better location welcome).

llvm-svn: 135438

to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424

llvm-svn: 135418

moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415

virtual registers are used. 

llvm-svn: 135403

llvm-svn: 135375

solution but it is a small step towards removing the horror that is
TargetAsmInfo.

llvm-svn: 135237

Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.

llvm-svn: 135219

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795

is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742

llvm-svn: 134730

- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

llvm-svn: 134671

llvm-svn: 134668

llvm-svn: 134661

llvm-svn: 134645

based on a modifier, split it into two functions.

llvm-svn: 134637

llvm-svn: 134633

llvm-svn: 134630

llvm-svn: 134629