Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354

defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

llvm-svn: 97348

but codegen'd differently.  This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something.  However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.

llvm-svn: 97345

llvm-svn: 97316

llvm-svn: 97313

llvm-svn: 97310

llvm-svn: 97295

of a subtle interation in a loop operating in densemap order.

llvm-svn: 97288

confusing the old MAT variable with the new GlobalType one.  This caused
us to promote the @disp global pointer into:

@disp.body = internal global double*** undef

instead of:

@disp.body = internal global [3 x double**] undef

llvm-svn: 97285

llvm-svn: 97283

llvm-svn: 97278

for alignment into the LSDA. If the TType base offset is emitted, then put the
padding there. Otherwise, put it in the call site table length. There will be no
conflict between the two sites when placing the padding in one place.

llvm-svn: 97277

o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]

llvm-svn: 97276

This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.

Also allow folding of memory operands on FMRSD.

llvm-svn: 97275

llvm-svn: 97269

The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

llvm-svn: 97262

llvm-svn: 97261

llvm-svn: 97259

as X86 is currently the only FastISel target.  Per review.

llvm-svn: 97255

llvm-svn: 97251

argument of createGVNPass and set it automatically for -O3.

llvm-svn: 97245

llvm-svn: 97235

stuff to emit optimal nops in the right places.

llvm-svn: 97233

present in the module.

llvm-svn: 97232

llvm-svn: 97231

llvm-svn: 97228

llvm-svn: 97227

Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.

llvm-svn: 97226

llvm-svn: 97220

object construction. There is no provision to change them when the 
code for a function generated. 
So we have to change these names while printing assembly.

llvm-svn: 97213

llvm-svn: 97211

llvm-svn: 97201

llvm-svn: 97200

the alignment requirement, if it no longer makes the TType base offset overflow
into extra bytes, then we need to pad to those bytes ourselves.

llvm-svn: 97196

llvm-svn: 97193

llvm-svn: 97192

will eliminate the need for padding in the "Call site table length". E.g., if
we have this:

    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0x7f  ## @TType base offset
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

with padding of 1. We want to emit the padding like this:
 
    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0xff  ## @TType base offset
        .space  1,0   ## Padding
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

and not with padding on the "Call site table length" entry.

llvm-svn: 97183

introduced when mallocinst was eliminated. 

llvm-svn: 97178

llvm-svn: 97169