Should fix llvm-gcc selfhost.

llvm-svn: 134699

We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

llvm-svn: 134695

- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.

llvm-svn: 134677

llvm-svn: 134671

llvm-svn: 134668

Fixes PR9602!

llvm-svn: 134665

processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664

llvm-svn: 134661

Part of PR10299 and rdar://9740322

llvm-svn: 134653

Fixes PR10149 and rdar://9738585

llvm-svn: 134648

llvm-svn: 134647

llvm-svn: 134645

llvm-svn: 134643

llvm-svn: 134641

llvm-svn: 134640

based on a modifier, split it into two functions.

llvm-svn: 134637

numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.

llvm-svn: 134635

llvm-svn: 134633

llvm-svn: 134630

llvm-svn: 134629

llvm-svn: 134628

llvm-svn: 134627

llvm-svn: 134626

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 134622

If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,

        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620

llvm-svn: 134617

llvm-svn: 134616

llvm-svn: 134614

multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609

llvm-svn: 134608

llvm-svn: 134606

llvm-svn: 134601

llvm-svn: 134599

llvm-svn: 134595

hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.

llvm-svn: 134592

Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

llvm-svn: 134590

llvm-svn: 134577

llvm-svn: 134572