precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235

llvm-svn: 190234

llvm-svn: 190232

into a 5-bit or 6-bit field.

llvm-svn: 190226

llvm-svn: 190224

llvm-svn: 190221

equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220

llvm-svn: 190219

llvm-svn: 190156

Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155

This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.

llvm-svn: 190154

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153

This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.

llvm-svn: 190152

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150

This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.

llvm-svn: 190148

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145

llvm-svn: 190144

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140

No functional change

llvm-svn: 190134

Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133

No functional change

llvm-svn: 190131

don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.

llvm-svn: 189727

has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.

llvm-svn: 189690

These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478

llvm-svn: 189476

llvm-svn: 189471

The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.

llvm-svn: 189468

[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri

llvm-svn: 189467

Also, fix predicates.

llvm-svn: 189432

No functionality change.

llvm-svn: 189431

llvm-svn: 189430

llvm-svn: 189396

llvm-svn: 189332

llvm-svn: 189330

llvm-svn: 189213