- Oct 11, 2011
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Craig Topper authored
llvm-svn: 141656
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Craig Topper authored
llvm-svn: 141654
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Craig Topper authored
llvm-svn: 141651
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Cameron Zwarich authored
lowering of NEON code. It provides little-to-no benefit now and only introduces additional complexity. llvm-svn: 141646
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Craig Topper authored
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
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Nick Lewycky authored
.symtab_shndx reading and writing together, and finally we have a testcase for r141440. llvm-svn: 141641
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Nick Lewycky authored
in st_shndx fields. llvm-svn: 141639
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Nick Lewycky authored
layer of abstraction around SymbolRef where you can read its private SymbolPimpl member. llvm-svn: 141636
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Andrew Trick authored
I'm not sure we will need it in the long run, but the option is currently useful for checking if the output of LSR is "clean". llvm-svn: 141634
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Andrew Trick authored
IVs. Indvars previously chose randomly between congruent IVs. Now it will bias the decision toward IVs that SCEVExpander likes to create. This was not done to fix any problem, it's just a welcome side effect of factoring code. llvm-svn: 141633
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Akira Hatanaka authored
that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. llvm-svn: 141623
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Jakob Stoklund Olesen authored
The VMOVS widening needs to look at the implicit COPY operands. Trying to dig out the COPY instruction from an iterator in copyPhysReg() is the wrong approach. The expandPostRAPseudo() hook gets to look at COPY instructions before they are converted to copyPhysReg() calls. llvm-svn: 141619
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Akira Hatanaka authored
Mips64. llvm-svn: 141618
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Lang Hames authored
llvm-svn: 141616
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Akira Hatanaka authored
llvm-svn: 141615
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Nick Lewycky authored
llvm-svn: 141614
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Akira Hatanaka authored
llvm-svn: 141613
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Akira Hatanaka authored
zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
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Tanya Lattner authored
Make it possible to use the linker without destroying the source module. This is so the source module can be linked to multiple other destination modules. For all that used LinkModules() before, they will continue to destroy the source module as before. This line, and those below, will be ignored-- M include/llvm/Linker.h M tools/bugpoint/Miscompilation.cpp M tools/bugpoint/BugDriver.cpp M tools/llvm-link/llvm-link.cpp M lib/Linker/LinkModules.cpp llvm-svn: 141606
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Nick Lewycky authored
If you want to tackle adding the testcase, let me know. It's a 4.2MB ELF file and I'll be happy to mail it to you. llvm-svn: 141605
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Akira Hatanaka authored
for 64-bit load and store instructions. Add definitions of 64-bit memory operand and 16-bit immediate operand. llvm-svn: 141603
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Bill Wendling authored
llvm-svn: 141602
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Lang Hames authored
promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. llvm-svn: 141599
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Michael J. Spencer authored
llvm-svn: 141597
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Devang Patel authored
llvm-svn: 141594
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Jim Grosbach authored
llvm-svn: 141592
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Bill Wendling authored
llvm-svn: 141591
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Jim Grosbach authored
llvm-svn: 141590
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Bill Wendling authored
block. E.g., if we have: movs r1, r1 rsb r1, 0 movs r2, r2 rsb r2, 0 we don't want this to be converted to: movs r1, r1 movs r2, r2 itt mi rsb r1, 0 rsb r2, 0 PR11107 & <rdar://problem/10259534> llvm-svn: 141589
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Eli Friedman authored
llvm-svn: 141585
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- Oct 10, 2011
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Michael J. Spencer authored
llvm-svn: 141581
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Jakob Stoklund Olesen authored
Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. llvm-svn: 141578
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Devang Patel authored
llvm-svn: 141576
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Benjamin Kramer authored
llvm-svn: 141571
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Nadav Rotem authored
instruction set has no 64-bit SRA support. llvm-svn: 141570
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Devang Patel authored
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. llvm-svn: 141569
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Bruno Cardoso Lopes authored
compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic llvm-svn: 141564
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Benjamin Kramer authored
llvm-svn: 141563
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Bill Wendling authored
hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
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Owen Anderson authored
llvm-svn: 141557
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