Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359

llvm-svn: 116348

a separate bit in the coding.

llvm-svn: 116347

llvm-svn: 116339

llvm-svn: 116338

llvm-svn: 116321

llvm-svn: 116318

ARM instructions.

llvm-svn: 116313

"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310

address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296

llvm-svn: 116284

llvm-svn: 116266

register operand.

llvm-svn: 116259

Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257

llvm-svn: 116251

llvm-svn: 116249

llvm-svn: 116240

leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232

llvm-svn: 116220

llvm-svn: 116218

Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217

matching in tblgen to do the predicate operand.

llvm-svn: 116213

llvm-svn: 116212

llvm-svn: 116201

llvm-svn: 116198

llvm-svn: 116197

llvm-svn: 116196

llvm-svn: 116195

llvm-svn: 116194

llvm-svn: 116143

llvm-svn: 116140

llvm-svn: 116136

llvm-svn: 116135

1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134

before decrementing. <rdar://problem/8529919>

llvm-svn: 116126

llvm-svn: 116123

concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112

''const'ify getMachineOpValue() and associated helpers.'

llvm-svn: 116067

llvm-svn: 116064

llvm-svn: 116059