llvm-svn: 6796

llvm-svn: 6765

* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes

llvm-svn: 6655

None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.

llvm-svn: 6549

SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
  only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
  return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
  requires a register-version opcode.

SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions

llvm-svn: 6548

llvm-svn: 6439

annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.

llvm-svn: 6371

llvm-svn: 5272

llvm-svn: 4359

llvm-svn: 4276

llvm-svn: 4132

since it is defined by the instruction.

llvm-svn: 3966

Added LDFSR, LDXFSR, STFSR and STXFSR.
Fixed operands info for RDCCR, WRCCR.

llvm-svn: 2835

llvm-svn: 1965

llvm-svn: 1304

llvm-svn: 1301

Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).

llvm-svn: 1120

llvm-svn: 1111

Add M_CC_FLAG for many instructions that use int or fp CC registers.

llvm-svn: 1006

which have the same opcode and operands but different flags.

llvm-svn: 938

llvm-svn: 681

Move contents of SparcMachineInstrDesc[] out of SparcInternals.h
into Sparc.cpp

llvm-svn: 644