to mark TableGen description files with "C++ mode".

llvm-svn: 7841

llvm-svn: 7565

llvm-svn: 7182

some comments.

llvm-svn: 7119

  the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
  actually assigned into the right portion of the instruction.

llvm-svn: 7074

llvm-svn: 6639

llvm-svn: 6618

llvm-svn: 6594

they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).

llvm-svn: 6564

* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).

llvm-svn: 6560

None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.

llvm-svn: 6549

Created new classes from which instructions inherit their ordering of fields.

llvm-svn: 6461

"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456

instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

llvm-svn: 6437

SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.

llvm-svn: 6429

* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr

llvm-svn: 6388