llvm-svn: 127496

llvm-svn: 127495

llvm-svn: 127493

llvm-svn: 127491

as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489

llvm-svn: 127488

and VDUPLN32d, respectively.

llvm-svn: 127486

as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485

llvm-svn: 127483

llvm-svn: 127482

the diagnostic.

llvm-svn: 127480

Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used.

llvm-svn: 127478

created from the", it broke some GCC test suite tests.

llvm-svn: 127477

llvm-svn: 127473

llvm-svn: 127471

llvm-svn: 127470

llvm-svn: 127469

Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text.

llvm-svn: 127468

other systems pending.

PR9456.

llvm-svn: 127466

ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.

Should fix the selfhost failures that started with r127463.

llvm-svn: 127465

InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.

Fixes PR9454.

llvm-svn: 127464

do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15!

llvm-svn: 127463

The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270

This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.

llvm-svn: 127462

lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459

CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456

llvm-svn: 127453

llvm-svn: 127448

llvm-svn: 127447

llvm-svn: 127446

llvm-svn: 127445

llvm-svn: 127442

corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.

llvm-svn: 127441

Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.

llvm-svn: 127440

llvm-svn: 127434

Value, not an Instruction, so casting is not necessary. Also,
it's theoretically possible that the Value is not an
Instruction, since WeakVH follows RAUWs.

llvm-svn: 127427

llvm-svn: 127426

after it has finished all of its reassociations, because its
habit of unlinking operands and holding them in a datastructure
while working means that it's not easy to determine when an
instruction is really dead until after all its regular work is
done. rdar://9096268.

llvm-svn: 127424

llvm-svn: 127423

llvm-svn: 127422

llvm-svn: 127420