Commits · 6646becd0c94fb2ead7b2b944f2f7ebf40d5d8ba · Roger Ferrer / llvm-epi-0.8 · GitLab

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Apr 03, 2018
- [x86] Extend my goofy SP offset scrubbing for llc test cases to actually · 6646becd
  Chandler Carruth authored Apr 03, 2018
  6646becd
- bpf: fix incorrect SELECT_CC lowering · d3b522f5
  Yonghong Song authored Apr 03, 2018
  d3b522f5
- [x86] Tidy up test case, generate check lines with script. NFC. · 72eb30f7
  Chandler Carruth authored Apr 03, 2018
  72eb30f7
- Align stubs for external and common global variables to pointer size. · 8c58750c
  Rafael Espindola authored Apr 02, 2018
  8c58750c
Apr 02, 2018
- [X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346 · 92746830
  Lama Saba authored Apr 02, 2018
  92746830
- [X86][Silvermont] Use correct latency and throughput information for divide... · 96729cd6
  Craig Topper authored Apr 02, 2018
  96729cd6
- [X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide. · 6a814904
  Craig Topper authored Apr 02, 2018
  6a814904
- [X86] Correct the throughput for divide instructions in Sandy... · 8104f266
  Craig Topper authored Apr 02, 2018
  8104f266
- [X86] Fix the SchedRW for AVX512 shift instructions. · dc740943
  Craig Topper authored Apr 02, 2018
  dc740943
- [X86] Add an itinerary to BTR64rr. · caec723a
  Craig Topper authored Apr 02, 2018
  caec723a
- [AArch64] Reserve x18 register on Fuchsia · 934e5d54
  Petr Hosek authored Apr 01, 2018
  934e5d54
Apr 01, 2018
- [X86] Check if the load and store are to the same pointer before preventing... · db6caabc
  Craig Topper authored Apr 01, 2018
  db6caabc
- [X86] Add test case to show failure to promote i16 subtract when the LHS is a... · 3998041e
  Craig Topper authored Apr 01, 2018
  3998041e
- [X86] Allow i16 subtracts to be promoted if the load is on the LHS and its not being stored. · ae2de57d
  Craig Topper authored Apr 01, 2018
  ae2de57d
- [X86] Add test case to show failure to promote i16 subtract because we... · 280f6313
  Craig Topper authored Apr 01, 2018
  280f6313
Mar 31, 2018
- [DAGCombine] (float)((int) f) --> ftrunc (PR36617) · 6124cae8
  Sanjay Patel authored Mar 31, 2018
  6124cae8
- [X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entries · 3b8ad346
  Simon Pilgrim authored Mar 31, 2018
  3b8ad346
- [MIR-Canon] Adding support for local idempotent instruction hoisting. · 57c4f38c
  Puyan Lotfi authored Mar 31, 2018
  57c4f38c
- [X86] Add SchedRW for PMULLD · 13a0f83a
  Craig Topper authored Mar 31, 2018
  13a0f83a
Mar 30, 2018
- [Hexagon] Fix testcase · 526fbf8e
  Krzysztof Parzyszek authored Mar 30, 2018
  526fbf8e
- [Hexagon] Avoid creating invalid offsets in packetizer · 0f983d69
  Krzysztof Parzyszek authored Mar 30, 2018
  0f983d69
- [MIR] Adding support for Named Virtual Registers in MIR. · 399b46c9
  Puyan Lotfi authored Mar 30, 2018
  399b46c9
- [AMDGPU] Fixed some instructions latencies · 74e2974a
  Stanislav Mekhanoshin authored Mar 30, 2018
  74e2974a
- [SelectionDAG] Removing FABS folding from DAGCombiner · e09b7dcf
  Sanjay Patel authored Mar 30, 2018
  e09b7dcf
- [Hexagon] Fix printing :mem_noshuf on compiler-generated packets · 46abcb23
  Krzysztof Parzyszek authored Mar 30, 2018
  46abcb23
- [AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE. · 59e5ef79
  Michael Bedy authored Mar 30, 2018
  59e5ef79
- [MachineCopyPropagation] Handle COPY with overlapping source/dest. · 208fe67a
  Eli Friedman authored Mar 30, 2018
  208fe67a
Mar 29, 2018
- AMDGPU: Support realigning stack · 03ae399d
  Matt Arsenault authored Mar 29, 2018
  03ae399d
- [X86] Correct the placement of ReadAfterLd in BEXTR and BZHI. Add dedicated SchedRW for BEXTR/BZHI. · 89310f56
  Craig Topper authored Mar 29, 2018
  89310f56
- AMDGPU: Increase default stack alignment · ffb132e7
  Matt Arsenault authored Mar 29, 2018
  ffb132e7
- AMDGPU: Fix selection error on constant loads with < 4 byte alignment · 6c041a3c
  Matt Arsenault authored Mar 29, 2018
  6c041a3c
- Try to fix a couple tests for Windows. · 407ff1b1
  Paul Robinson authored Mar 29, 2018
  407ff1b1
- Reapply "[DWARFv5] Emit file 0 to the line table." · b271f31d
  Paul Robinson authored Mar 29, 2018
  b271f31d
- [Hexagon] Add support to handle bit-reverse load intrinsics · dc7a557e
  Krzysztof Parzyszek authored Mar 29, 2018
  dc7a557e
Mar 28, 2018
- [PostRAMachineSink] preserve CFG · f90fe701
  Jun Bum Lim authored Mar 28, 2018
  f90fe701
- [Hexagon] Add support for "new" circular buffer intrinsics · 440ba3ae
  Krzysztof Parzyszek authored Mar 28, 2018
  440ba3ae
- [MachineOutliner] Simplify call outlining + require valid callee save info for call outlining · 4aa14dbc
  Jessica Paquette authored Mar 28, 2018
  4aa14dbc
- [X86][AVX2] Add shuffle test case from PR36933 · 7237e0cf
  Simon Pilgrim authored Mar 28, 2018
  7237e0cf
- Revert "Reapply "[DWARFv5] Emit file 0 to the line table."" · 202f8094
  Alexander Potapenko authored Mar 28, 2018
  202f8094
- Revert "[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader" · cdac172e
  Tim Renouf authored Mar 28, 2018
  cdac172e