begin at DEF slots. Fixes the second half of PR8813.

llvm-svn: 122225

llvm-svn: 122224

the register; it may be a dead def instead. Fixes PR8820.

llvm-svn: 122218

PR8822.

llvm-svn: 122207

half of PR8813.

llvm-svn: 122205

llvm-svn: 122199

createMachineVerifierPass and MachineFunction::verify.

The banner is printed before the machine code dump, just like the printer pass.

llvm-svn: 122113

the operand uses the same register as a tied operand:

  %r1 = add %r1, %r1

If add were a three-address instruction, kill flags would be required on at
least one of the uses. Since it is a two-address instruction, the tied use
operand must not have a kill flag.

This change makes the kill flag on the untied use operand optional.

llvm-svn: 122082

operands in a variadic instruction.

llvm-svn: 119446

(and likely) wrong about anyhow.

llvm-svn: 119320

It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.

llvm-svn: 117981

At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960

When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944

llvm-svn: 117762

multiplicity.

llvm-svn: 117630

llvm-svn: 117602

Only virtuals should be requires to be connected.

llvm-svn: 117422

components, each should get its own virtual register.

llvm-svn: 117407

SlotIndexes when available.

llvm-svn: 117392

llvm-svn: 117391

Magic is happening that we don't understand.

llvm-svn: 117370

of all predecessors.

llvm-svn: 117191

llvm-svn: 117170

unconditional branch.

llvm-svn: 117041

Get rid of static constructors for pass registration.  Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820

llvm-svn: 115996

llvm-svn: 115874

llvm-svn: 115408

Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API.

llvm-svn: 111815

llvm-svn: 111540

llvm-svn: 110460

llvm-svn: 110454

When a physical register is in use, some alias of that register has a live
interval with a relevant live range. That is the sad state of intervals after
physreg coalescing of subregs, and it is good enough for correct register
allocation.

llvm-svn: 110452

llvm-svn: 110410

LiveVariables becomes horribly wrong while the coalescer is running, but the
analysis is not zapped until after the coalescer pass has run. This causes tons
of false reports when calling verify form the coalescer.

llvm-svn: 110402

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.

Stuff we don't check yet:

- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?

llvm-svn: 110386

be killed before being redefined.

These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.

llvm-svn: 110362

- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344

The old approach was wrong. It had an off-by-one error.

llvm-svn: 104034